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[VHDL-FPGA-Verilog] fpu_double

Description: The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard for double precision floating point arithmetic.
Platform: | Size: 244736 | Author: 丁一 | Hits:

[Other] Area-Delay-Power-Efficient-Carry-Select-Adder-usi

Description: Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com
Platform: | Size: 610304 | Author: anandg | Hits:

[VHDL-FPGA-Verilog] adder

Description: 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Platform: | Size: 5219328 | Author: 无聊人 | Hits:

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[VHDL-FPGA-Verilog] fpu_double

[Other] Area-Delay-Power-Efficient-Carry-Select-Adder-usi

[VHDL-FPGA-Verilog] adder

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